1) Field of the Invention
The present invention relates to an MOS (Metal Oxide Semiconductor) field effect transistor that has a thin film SOI (Silicon On Insulator) structure, and a method of manufacturing the MOS field effect transistor.
2) Description of the Related Art
For faster information processing and data communication and lower power consumption, there are demands for MOS field effect transistors with enhanced performances which ensures a faster operation with a low leak current. To enhance performances of the MOS field effect transistors at a low cost by miniaturization of the structure, however, the structure must be optimized in consideration of various elements.
To prevent degradation of the performances due to miniaturization, the gate length should be shortened. Reducing the gate length, however, increases a so-called short-channel effect, which reduces the threshold and a source-drain breakdown voltage of a transistor with a decrease in the gate length, thereby increasing a sub threshold value.
To realize a transistor with an excellent characteristic by suppressing the short-channel effect, it is generally necessary to increase impurity concentration of a channel portion according to a decrease in the gate length and increase impurity concentrations of the source/drain regions for a lower parasitic resistance. This leads to an increase in a pn junction capacitance of the source/drain regions and an increase in charge/discharge time of a parasitic capacitor, both of which hinder an improvement in the operation speed.
There is a semiconductor using a substrate having an SOI structure as one which can reduce the pn junction capacitance to increase the operation speed. The SOI structure has a silicon layer (SOI) laminated on a buried oxide film. A thin film SOI structure having a thin SOI layer, in particular, can improve the mobility greatly and reduce the parasitic capacitance significantly, thereby increasing a drive current of the transistor significantly.
For example, Japanese Patent Application Laid-Open No. H5-160404 discloses a technique of forming a thin film transistor thin enough to accomplish complete depletion of a channel region of a silicon (Si) layer and thick enough at a source region and a drain region outside the channel region not to cause spiking of a contact hole.
Japanese Patent Application Laid-Open No. 2003-174161 discloses a technique of improving the performances of MOS transistors by forming a buried oxide in an Si substrate and depositing an SiGeC crystal on Si on the buried oxide.
Since in the thin film SOI structure, an SOI substrate with a uniform SOI film thickness is prepared using complicated manufacture processes, it suffers a high substrate cost and a high manufacture cost. In particular, a thin film SOI substrate of a complete depletion type which is expected to have a significant characteristic improvement becomes very expensive. In the complete depletion type thin film SOI structure, a parasitic part and the channel become thinner, thus making it difficult to reduce the parasitic resistance.